Multistage networks (e.g., Omega networks, Clos networks, Butterfly networks, Banyan networks, etc.) allow for a large number of hosts to connect with each other by implementing multiple switching layers using smaller switching elements. Multistage networks can be highly fault-tolerant and reliable when multiple switches are linked to allow for redundant paths between multiple source and destination pairs.
On-chip networks that connect multiple processor tiles on the same chip are typically implemented using a rectangular topology. A rectangular topology is easy to layout and requires only point-to-point links between physically adjacent tiles on the chip. The replication of identical logic blocks in the form of a two-dimensional array can be referred to as “tiled architecture” and has recently emerged as a new trend in the multi-core processor space.